A multiplier adder combining a multiplier that multiplies first and second inputs and an adder that adds or subtracts (referred together to “adds” hereafter) a third input to or from the multiplication result is available as an arithmetic unit. Meanwhile, a floating point multiplier adder implements a digit alignment operation to align decimal point positions of floating point inputs, and performs a normalization shift on a multiplication addition result.
A normalization shift is an operation to return a decimal point position of a multiplication addition result to a predetermined position by shifting the decimal point position left, and is performed by a normalization shift circuit for shifting a multiplication addition result left. When the point position of the multiplication addition result is known, a normalization shift amount, or in other words a left shift amount, can be determined, but when the normalization shift amount is determined after waiting for an addition result, a delay occurs in the operation time. Therefore, a normalization shift amount prediction circuit is provided to predict the normalization shift amount from the input into the adder and so on.
The normalization shift amount predicted by the normalization shift amount prediction circuit is not always the correct shift amount. The reason for this is that the normalization shift amount prediction circuit does not accurately take into account carry propagation from the least significant digit. When the predicted shift amount is smaller than the correct shift amount, the normalization shift circuit corrects the prediction error by implementing an additional left shift. When the predicted shift amount is larger than the correct shift amount, on the other hand, since the normalization shift circuit does not have a right shift function, a right shift correction circuit for shifting the output of the normalization shift circuit right is used.
Japanese Laid-open Patent Publication No. H06-75752, Japanese Laid-open Patent Publication No. H08-87399, and Japanese Laid-open Patent Publication No. H10-289096 describe normalization shifts implemented on an addition result from an adder or the like.